The present disclosure relates generally to an integrated circuit (IC) device and, more particularly, to a method for forming a gate structure.
As technology nodes shrink, in some IC designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. Providing metal gate structures (e.g., including a metal gate electrode rather than polysilicon) offers one solution. One process of forming a metal gate stack is termed a “gate last” process in which the final gate stack is fabricated “last,” which allows for reduced number of subsequent processes that must be performed after formation of the gate, including high temperature processing. Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. In order to reduce gate leakage, high dielectric constant (high-k) gate insulator layers are also used, which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a typical gate oxide used in larger technology nodes.
There are challenges to implement such features and processes in CMOS fabrication. As technology nodes continue to decrease, particularly to 22-nanometer technology nodes and beyond, the spacing between gate stacks continues to decrease. A high aspect ratio results when the spacing between gate stacks is decreased. The high aspect ratio will cause shadowing effects when forming pocket/lightly doped source/drain (LDD) regions by using tilt-angle implanting processes. Hence, it will affect the pocket/LDD formation process.